1 258 Posti di lavoro per Design Verification in Italia

Principal Digital Design Verification Engineer - CMOS Image Sensors / UVM / Python / Perl Do you have solid experience in the design and verification domain, preferably with CMOS Image Sensors? Excellent expertise in UVM / digital verification methodology? Want to work in beautiful northern Italy? If so, then this could be the one for you! We are seeking a Principal Digital Design Verification Engineer to join a globally known tech company's Design Centre in Trento in Italy on a permanent basis. As a Principal Digital Design Verification Engineer, you will lead Digital Design Verification projects, including planning and organizing work for contributors, and reporting the progress to managers and you will develop and consolidate new design verification flows, with the main target of developing state-of-the-art methodology and step up the efficiency across sites (amongst numerous other tasks) The role offers Hybrid working (up to 40% home office), pays a very competitive base salary, plus bonus, and an extensive benefits package. Please note, this role requires you to be a commutable distance from the office in Trento so kindly only apply if you are able to agree to this. We are also not able to consider applicants requiring a visa sponsor for Italy. If you do not possess the Right to Work in Italy, your application will not be processed. What do we look for? A background in technical, electronics, semiconductor, or physics, with a PhD / MSc in Engineering or Physics or equivalent experience. Solid experience in the design and verification domain, preferably with CMOS Image Sensors. Excellent expertise in UVM / digital verification methodology. Proficient in common scripting languages (Python, Perl, Tcl / shell, Makefile, etc.). Excellent communication and coordination skills. If this sounds interesting and you'd like to learn more, click the link below to apply or email me with a copy of your CV on By applying to this role you understand that we may collect your personal data and store and process it on our systems. For more information please see our Privacy Notice ( / >

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Digital Verification Engineer - Trento

We are currently looking for a talented and experienced Senior Digital Verification Engineer to join an innovative and dynamic Digital Design team. As a Senior Digital Verification Engineer, you will play a key role in leading the verification of digital designs for complex systems, working on cutting-edge projects in the semiconductor industry. You will be instrumental in developing and refining verification methodologies, as well as driving best practices in verification processes across multiple sites.

Working for a global brand, with beautiful offices set in the foothills of the mountain ranges in Trento, northern Italy. You will be part of a cutting edge R&D team focussed on the design, development and verification of CMOS image sensors.

Responsibilities:

• Lead Digital Design Verification projects, managing work allocation for contributors and reporting progress to senior management.
• Develop and refine advanced verification methodologies to improve efficiency across sites, ensuring the highest standards of quality.
• Analyse design specifications to create comprehensive verification plans for complex digital blocks and system components.
• Maintain and manage a digital regression environment, ensuring high functional and code coverage.
• Debug tests autonomously, collaborating effectively with designers to resolve issues.
• Write, integrate, and debug analogue models to support AMS verification teams.
• Contribute to the development of verification methodologies for imaging systems and system model integration (e.g., SystemC).
• Apply Continuous Integration (CI) principles, working with tools like Jenkins to optimise workflows.
• Collaborate with teams across Europe and Japan to align verification strategies and share knowledge on best practices.

Key Requirements:

• A strong technical background in electronics, semiconductor technology, or physics, with a PhD/MSc in Engineering, Physics, or a related field, or equivalent professional experience.
• Significant experience in the digital verification domain, preferably with expertise in CMOS Image Sensors.
• Advanced knowledge of UVM (Universal Verification Methodology) and digital verification processes.
• Proficiency in scripting languages such as Python, Perl, Tcl/shell, or Makefile.
• Strong communication and coordination skills, with the ability to work effectively with both internal teams and external contractors.
• Proven experience working with cross-functional, multi-national, and remote teams.
• Fluency in English, both written and spoken.

Email -

Tel - 01189073075

LinkedIn -

Digital Verification Engineer - Trento

We are currently looking for a talented and experienced Senior Digital Verification Engineer to join an innovative and dynamic Digital Design team. As a Senior Digital Verification Engineer, you will play a key role in leading the verification of digital designs for complex systems, working on cutting-edge projects in the semiconductor industry. You will be instrumental in developing and refining verification methodologies, as well as driving best practices in verification processes across multiple sites.

Working for a global brand, with beautiful offices set in the foothills of the mountain ranges in Trento, northern Italy. You will be part of a cutting edge R&D team focussed on the design, development and verification of CMOS image sensors.

Responsibilities:

• Lead Digital Design Verification projects, managing work allocation for contributors and reporting progress to senior management.
• Develop and refine advanced verification methodologies to improve efficiency across sites, ensuring the highest standards of quality.
• Analyse design specifications to create comprehensive verification plans for complex digital blocks and system components.
• Maintain and manage a digital regression environment, ensuring high functional and code coverage.
• Debug tests autonomously, collaborating effectively with designers to resolve issues.
• Write, integrate, and debug analogue models to support AMS verification teams.
• Contribute to the development of verification methodologies for imaging systems and system model integration (e.g., SystemC).
• Apply Continuous Integration (CI) principles, working with tools like Jenkins to optimise workflows.
• Collaborate with teams across Europe and Japan to align verification strategies and share knowledge on best practices.

Key Requirements:

• A strong technical background in electronics, semiconductor technology, or physics, with a PhD/MSc in Engineering, Physics, or a related field, or equivalent professional experience.
• Significant experience in the digital verification domain, preferably with expertise in CMOS Image Sensors.
• Advanced knowledge of UVM (Universal Verification Methodology) and digital verification processes.
• Proficiency in scripting languages such as Python, Perl, Tcl/shell, or Makefile.
• Strong communication and coordination skills, with the ability to work effectively with both internal teams and external contractors.
• Proven experience working with cross-functional, multi-national, and remote teams.
• Fluency in English, both written and spoken.

Email -

Tel - 01189073075

LinkedIn -

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22.08.2025

06.10.2025

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Role

The Chips-IT Foundation is seeking an experienced Verification Engineer to support the development and validation of advanced digital IPs and System-on-Chip (SoC) platforms. The role focuses on creating and maintaining verification environments using industry-standard methodologies (e.g., UVM), ensuring functional correctness of designs from specification to tape-out. The position also involves collaboration with design, architecture, and software teams to deliver reliable and high-quality silicon. The work can be carried out either in Pavia or in Bologna.

Key Responsibilities:

• Define and implement verification strategies at IP and SoC levels.
• Develop and maintain UVM-based verification environments, including testbenches and functional coverage.
• Design and execute test plans aligned with design specifications and requirements.
• Debug RTL and simulation issues using advanced tools and techniques.
• Integrate verification components and ensure complete test coverage.
• Contribute to regression infrastructure and manage automated test execution.
• Collaborate closely with RTL designers, DFT engineers, and physical implementation teams.
• Support post-silicon bring-up and validation activities as needed.

Required Qualifications:

• Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• At least 5 years of experience in digital design verification.
• Strong knowledge of SystemVerilog and UVM methodology.
• Hands-on experience with simulation and debug tools (e.g., QuestaSim, VCS, Verdi).
• Familiarity with industry-standard protocols such as AMBA AXI, APB, and AHB.
• Experience in writing constrained-random testbenches and analyzing coverage metrics.
• Good understanding of digital design, SoC architecture, and RTL development.
• Strong teamwork, communication, and documentation skills.

What we offer

• Competitive compensation and contract type, to be negotiated based on qualifications and experience
• Lunch tickets
• Private health care coverage depending on your role and contract
• Structured growth path, with ongoing access to training and updates
• Networking opportunities with industry-leading professionals
• International environment
• Tax deductions: Candidates from abroad, comprising Italian citizens, who have carried scientific research activity abroad and meet specific requirements, may be entitled to a taxable income deduction up to 90% for a period of 6 to 13 years

The Foundation “Italian Center for the Design of Semiconductor Integrated Circuits,” also known as the Chips-IT Foundation, is a nonprofit research and technology organization under the supervision of the Ministries of Industry.

The Foundation is Italy's first RTO (Research and Technology Organization) vertically focused on semiconductor research and stands as a center of excellence in frontier research on semiconductor design, as well as a pivotal center of the Italian semiconductor ecosystem and expertise.

Missions of the Foundation:

• promote the design and development of integrated circuits
• strengthen the system of professional training in the field of microelectronics
• ensure the establishment of a network of universities, research centers and enterprises that fosters innovation and technology transfer in the field

Disclaimer

No ranking list or list of suitable candidates will be prepared and published.

The Foundation reserves the right to:

a. extend or reopen the deadline of this notice;

b. revoke this notice;

c. not make any selection from among the applications submitted if they are deemed not to meet the functions set forth in the notice;

without any claims or rights being asserted by the interested parties.

Social network you want to login/join with:

The Chips-IT Foundation is seeking an experienced Verification Engineer to support the development and validation of advanced digital IPs and System-on-Chip (SoC) platforms. The role focuses on creating and maintaining verification environments using industry-standard methodologies (e.g., UVM), ensuring functional correctness of designs from specification to tape-out. The position also involves collaboration with design, architecture, and software teams to deliver reliable and high-quality silicon. The work can be carried out either in Pavia or in Bologna.

Key Responsibilities:

• Define and implement verification strategies at IP and SoC levels.
• Develop and maintain UVM-based verification environments, including testbenches and functional coverage.
• Design and execute test plans aligned with design specifications and requirements.
• Debug RTL and simulation issues using advanced tools and techniques.
• Integrate verification components and ensure complete test coverage.
• Contribute to regression infrastructure and manage automated test execution.
• Collaborate closely with RTL designers, DFT engineers, and physical implementation teams.
• Support post-silicon bring-up and validation activities as needed.

Required Qualifications:

• Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• At least 5 years of experience in digital design verification.
• Strong knowledge of SystemVerilog and UVM methodology.
• Hands-on experience with simulation and debug tools (e.g., QuestaSim, VCS, Verdi).
• Familiarity with industry-standard protocols such as AMBA AXI, APB, and AHB.
• Experience in writing constrained-random testbenches and analyzing coverage metrics.
• Good understanding of digital design, SoC architecture, and RTL development.
• Strong teamwork, communication, and documentation skills.

What we offer

• Competitive compensation and contract type, to be negotiated based on qualifications and experience
• Lunch tickets
• Private health care coverage depending on your role and contract
• Structured growth path, with ongoing access to training and updates
• Networking opportunities with industry-leading professionals
• International environment
• Tax deductions: Candidates from abroad, comprising Italian citizens, who have carried scientific research activity abroad and meet specific requirements, may be entitled to a taxable income deduction up to 90% for a period of 6 to 13 years

The Foundation “Italian Center for the Design of Semiconductor Integrated Circuits,” also known as the Chips-IT Foundation, is a nonprofit research and technology organization under the supervision of the Ministries of Industry.

The Foundation is Italy's first RTO (Research and Technology Organization) vertically focused on semiconductor research and stands as a center of excellence in frontier research on semiconductor design, as well as a pivotal center of the Italian semiconductor ecosystem and expertise.

Missions of the Foundation:

• promote the design and development of integrated circuits
• strengthen the system of professional training in the field of microelectronics
• ensure the establishment of a network of universities, research centers and enterprises that fosters innovation and technology transfer in the field

Disclaimer

No ranking list or list of suitable candidates will be prepared and published.

The Foundation reserves the right to:

a. extend or reopen the deadline of this notice;

b. revoke this notice;

c. not make any selection from among the applications submitted if they are deemed not to meet the functions set forth in the notice;

without any claims or rights being asserted by the interested parties.

Social network you want to login/join with:

The Chips-IT Foundation is seeking an experienced Verification Engineer to support the development and validation of advanced digital IPs and System-on-Chip (SoC) platforms. The role focuses on creating and maintaining verification environments using industry-standard methodologies (e.g., UVM), ensuring functional correctness of designs from specification to tape-out. The position also involves collaboration with design, architecture, and software teams to deliver reliable and high-quality silicon. The work can be carried out either in Pavia or in Bologna.

Key Responsibilities:

• Define and implement verification strategies at IP and SoC levels.
• Develop and maintain UVM-based verification environments, including testbenches and functional coverage.
• Design and execute test plans aligned with design specifications and requirements.
• Debug RTL and simulation issues using advanced tools and techniques.
• Integrate verification components and ensure complete test coverage.
• Contribute to regression infrastructure and manage automated test execution.
• Collaborate closely with RTL designers, DFT engineers, and physical implementation teams.
• Support post-silicon bring-up and validation activities as needed.

Required Qualifications:

• Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• At least 5 years of experience in digital design verification.
• Strong knowledge of SystemVerilog and UVM methodology.
• Hands-on experience with simulation and debug tools (e.g., QuestaSim, VCS, Verdi).
• Familiarity with industry-standard protocols such as AMBA AXI, APB, and AHB.
• Experience in writing constrained-random testbenches and analyzing coverage metrics.
• Good understanding of digital design, SoC architecture, and RTL development.
• Strong teamwork, communication, and documentation skills.

What we offer

• Competitive compensation and contract type, to be negotiated based on qualifications and experience
• Lunch tickets
• Private health care coverage depending on your role and contract
• Structured growth path, with ongoing access to training and updates
• Networking opportunities with industry-leading professionals
• International environment
• Tax deductions: Candidates from abroad, comprising Italian citizens, who have carried scientific research activity abroad and meet specific requirements, may be entitled to a taxable income deduction up to 90% for a period of 6 to 13 years

The Foundation “Italian Center for the Design of Semiconductor Integrated Circuits,” also known as the Chips-IT Foundation, is a nonprofit research and technology organization under the supervision of the Ministries of Industry.

The Foundation is Italy's first RTO (Research and Technology Organization) vertically focused on semiconductor research and stands as a center of excellence in frontier research on semiconductor design, as well as a pivotal center of the Italian semiconductor ecosystem and expertise.

Missions of the Foundation:

• promote the design and development of integrated circuits
• strengthen the system of professional training in the field of microelectronics
• ensure the establishment of a network of universities, research centers and enterprises that fosters innovation and technology transfer in the field

Disclaimer

No ranking list or list of suitable candidates will be prepared and published.

The Foundation reserves the right to:

a. extend or reopen the deadline of this notice;

b. revoke this notice;

c. not make any selection from among the applications submitted if they are deemed not to meet the functions set forth in the notice;

without any claims or rights being asserted by the interested parties.

Role

The Chips-IT Foundation is seeking an experienced Verification Engineer to support the development and validation of advanced digital IPs and System-on-Chip (SoC) platforms. The role focuses on creating and maintaining verification environments using industry-standard methodologies (e.g., UVM), ensuring the functional correctness of designs from specification to tape-out. The position involves collaboration with design, architecture, and software teams to deliver reliable and high-quality silicon. Work can be carried out either in Pavia or Bologna.

Key Responsibilities :

• Define and implement verification strategies at IP and SoC levels.
• Develop and maintain UVM-based verification environments, including testbenches and functional coverage.
• Design and execute test plans aligned with design specifications and requirements.
• Debug RTL and simulation issues using advanced tools and techniques.
• Integrate verification components and ensure complete test coverage.
• Contribute to regression infrastructure and manage automated test execution.
• Collaborate closely with RTL designers, DFT engineers, and physical implementation teams.
• Support post-silicon bring-up and validation activities as needed.

Required Qualifications :

• Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• At least 5 years of experience in digital design verification.
• Strong knowledge of SystemVerilog and UVM methodology.
• Hands-on experience with simulation and debug tools (e.g., QuestaSim, VCS, Verdi).
• Familiarity with industry-standard protocols such as AMBA AXI, APB, and AHB.
• Experience in writing constrained-random testbenches and analyzing coverage metrics.
• Good understanding of digital design, SoC architecture, and RTL development.
• Strong teamwork, communication, and documentation skills.

What we offer

• Competitive compensation and contract type, to be negotiated based on qualifications and experience.
• Lunch tickets.
• Private health care coverage depending on your role and contract.
• Structured growth path, with ongoing access to training and updates.
• Networking opportunities with industry-leading professionals.
• International environment.
• Hybrid work policy.
• Tax deductions: Candidates from abroad, including Italian citizens who have carried out scientific research activity abroad and meet specific requirements, may be entitled to a taxable income deduction up to 90% for a period of 6 to 13 years.

About Fondazione Chips-IT

The Foundation “Italian Center for the Design of Semiconductor Integrated Circuits,” also known as the Chips-IT Foundation, is a nonprofit research and technology organization under the supervision of the Ministries of Industry.

The Foundation is Italy's first RTO (Research and Technology Organization) focused on semiconductor research and is a center of excellence in frontier research on semiconductor design, playing a pivotal role in the Italian semiconductor ecosystem and expertise.

Missions of the Foundation :

• Promote the design and development of integrated circuits.
• Strengthen the system of professional training in the field of microelectronics.
• Establish a network of universities, research centers, and enterprises that fosters innovation and technology transfer in the field.

Disclaimer

No ranking list or list of suitable candidates will be published. The Foundation reserves the right to :

• Extend or reopen the deadline of this notice.
• Revoke this notice.
• Not make any selection if applications do not meet the requirements.

Non verrà redatta e pubblicata alcuna graduatoria o elenco degli idonei. La Fondazione si riserva la facoltà di :

• Prorogare o riaprire il termine di scadenza del presente avviso.
• Revocare il presente avviso.
• Non procedere ad alcuna scelta tra le candidature presentate, ove ritenute non rispondenti alle funzioni di cui all’avviso.

Without claims or rights being asserted by interested parties.

Role

The Chips-IT Foundation is seeking an experienced Verification Engineer to support the development and validation of advanced digital IPs and System-on-Chip (SoC) platforms. The role focuses on creating and maintaining verification environments using industry-standard methodologies (e.g., UVM), ensuring functional correctness of designs from specification to tape-out. The position can be based in Pavia or Bologna.

Key Responsibilities:

• Define and implement verification strategies at IP and SoC levels.
• Develop and maintain UVM-based verification environments, including testbenches and functional coverage.
• Design and execute test plans aligned with design specifications and requirements.
• Debug RTL and simulation issues using advanced tools and techniques.
• Integrate verification components and ensure complete test coverage.
• Contribute to regression infrastructure and manage automated test execution.
• Collaborate closely with RTL designers, DFT engineers, and physical implementation teams.
• Support post-silicon bring-up and validation activities as needed.

Required Qualifications:

• Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• At least 5 years of experience in digital design verification.
• Strong knowledge of SystemVerilog and UVM methodology.
• Hands-on experience with simulation and debug tools (e.g., QuestaSim, VCS, Verdi).
• Familiarity with industry-standard protocols such as AMBA AXI, APB, and AHB.
• Experience in writing constrained-random testbenches and analyzing coverage metrics.
• Good understanding of digital design, SoC architecture, and RTL development.
• Strong teamwork, communication, and documentation skills.

What we offer:

• Competitive compensation and contract type, to be negotiated based on qualifications and experience.
• Lunch tickets.
• Private health care coverage depending on your role and contract.
• Structured growth path, with ongoing access to training and updates.
• Networking opportunities with industry-leading professionals.
• International environment.
• Hybrid work policy.
• Tax deductions: Candidates from abroad, including Italian citizens who have conducted scientific research activity abroad and meet specific requirements, may be entitled to a taxable income deduction up to 90% for a period of 6 to 13 years.

About Fondazione Chips-IT:

The Foundation “Italian Center for the Design of Semiconductor Integrated Circuits,” also known as the Chips-IT Foundation, is a nonprofit research and technology organization under the supervision of the Ministries of Industry.

The Foundation is Italy's first RTO (Research and Technology Organization) focused on semiconductor research and serves as a center of excellence in frontier research on semiconductor design, as well as a key player in the Italian semiconductor ecosystem.

Missions of the Foundation:

• Promote the design and development of integrated circuits.
• Strengthen professional training in the microelectronics field.
• Establish a network of universities, research centers, and enterprises to foster innovation and technology transfer.

Disclaimer:

No ranking list or list of suitable candidates will be published. The Foundation reserves the right to extend or reopen the application deadline, revoke this notice, or not select any candidates if they do not meet the requirements, without any claims from applicants.

• Verification of sub-systems using leading-edge verification methodologies.
• Experience with the development of verification plans and verification environments from scratch on multiple projects.
• Verification of blocks using System Verilog and UVM.
• Should have worked on scoreboard assertions, functional coverage, and formal verification, to reach verification goals
• Take complete ownership of a complex feature verification and mentor & guide junior verification engineers.
• Define and implement improvements in verification flow and methodology.
• Gate-level simulations and debugging at the sub-system level.
  
  

• Bachelor's or Master’s degree in Electronics Engineering with 8+ years of experience in digital design, of which at least 3 years in digital verification.
• Expertise in Verilog, System Verilog, UVM, object-oriented programming, scripting, and automation with Perl or Python.
• Firm understanding of constrained random functional verification, coverage, and assertions.
• Expertise in test plan development and development of verification environments from the ground up.
• Extensive experience with verification of complex blocks, regressions, and coverage closure.
• Experience with gate-level simulations and debugging.
• Excellent debugging, analytical, and problem-solving skills.
• Strong interpersonal, teamwork, and communication skills.
• Expected to be highly independent, proactive, and result-oriented to achieve verification goals.
  
  

• Knowledge of PMBus, SPI, OTP/MTP, and I2C protocols.
• Experience in technically mentoring and coaching junior engineers.